Resin sealed semiconductor device for use in testing and evaluation method of stress due to resin seal
US5204540A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1991 |
| Grant date | Apr 20, 1993 |
| Priority date | — |
| Expiry date | Mar 21, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A resin sealed semiconductor device for use in testing is disclosed, in which a first MOS field effect transistor is formed in a region within 100 .mu.m from an outer perimeter of a main surface of a silicon substrate, and a second MOS field effect transistor is formed in a region 100 .mu.m or more distant from an outer perimeter of the main surface, and the first and second MOS field effect transistors are encapsulated with resin. Dimensions and materials of the first MOS field effect transistor and the second MOS field effect transistor are identical. By comparing the electric characteristics of the first MOS field effect transistor and the electric characteristics of the second MOS field effect transistor, the effect produced on the MOS field effect transistors by the mechanical stresses due to the resin seal applied from a side direction of silicon substrate can be evaluated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.