Bus apparatus having hold registers for parallel processing in a microprocessor
US5204828A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 1991 |
| Grant date | Apr 20, 1993 |
| Priority date | — |
| Expiry date | Dec 3, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a microprocessor having a floating-point execution unit, a floating-point bus control apparatus for performing dual-operation instructions includes a multiplier unit having first and second multiplexed operand inputs, an adder unit also having first and second multiplexed operand inputs, a register for storing real and imaginary components of a constant, another register for storing an intermediate result of the multiplier unit and appropriate interconnections. The floating-point unit of the processor supplies first and second instruction source operands and a destination floating-point register. Multiplexers are used to select which operands are to be input to the appropriate operand inputs so as to implement the corresponding dual-operation algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.