EPROM virtual ground array
US5204835A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 13, 1990 |
| Grant date | Apr 20, 1993 |
| Priority date | — |
| Expiry date | Jun 13, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically programmable read only memory contains alternating metal bit lines and diffused bit lines. Each diffused bit line is broken into a plurality of segments. Each of the segments of the diffused bit line comprises a virtual source. A multiplicity of floating gate transistors are arranged in rows and columns. The floating gate transistors in each column are divided into M groups of N floating gate transistors each. The floating gate transistors in the n.sup.th and the (n+1).sup.th columns, where n is an odd integer given by 1.ltoreq.n.ltoreq.N and (N+1) is the maximum number of columns in the array are connected to the segments of one diffused bit line placed between the n.sup.th and the (n+1).sup.th columns. At least one first transfer transistor is arranged to connect one segment comprising a virtual source to a first metal bit line. The first metal bit line functions as the source for the N floating gate transistors in the (n+1).sup.th column connected to said one segment. At least one second transfer transistor connects the same one segment comprising a virtual source to a second metal bit line. The second metal bit line functions as a source for the N floating gate …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.