Method for fabricating bipolar and CMOS devices in integrated circuits using contact metallization for local interconnect and via landing
US5208170A · kind A · utility
29Cited by
11References
2Claims
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Key dates
| Filing date | Sep 18, 1991 |
| Grant date | May 4, 1993 |
| Priority date | — |
| Expiry date | Sep 18, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76889
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating bipolar and CMOS devices in integrated circuits using W as a local interconnect and via landing pad for bipolar and CMOS devices. The method includes the forming of an oxide/silicon bilayer above a local interconnect of tungsten/titanium wherein the oxide is patterned as a mask for the silicon/tungsten/titanium reactive ion etch, and the silicon layer above the tungsten/titanium layer is used as an etch stop for a via etch. The silicon layer is then reacted and converted to titanium silicide after the via etch to provide a low resistance path in the via from the local interconnect in a self aligned manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.