Double spacer salicide MOS device and method
US5208472A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1992 |
| Grant date | May 4, 1993 |
| Priority date | — |
| Expiry date | Jun 3, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
A method of forming a self-aligned metal oxide semiconductor (MOS) structure is described. Multilayer dielectrics are used at the edge of the gate electrode, and the gate electrode, the source and the drain have metal silicide regions. The first layer of dielectric is used to define a lightly doped drain (LDD) structure and the second dielectric layer serves to extend the oxide region at the gate edge and to improve the source/drain junction leakage property and to reduce the shorting percentage of gate to source/drain. A special device structure with extended lateral diffusion of junction under the oxide at the gate edge will be performed by using this method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.