Flat panel display in which low-voltage row and column address signals control a much pixel activation voltage
US5210472A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1992 |
| Grant date | May 11, 1993 |
| Priority date | — |
| Expiry date | Apr 7, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0809
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A flat panel display in which low-voltage row and column address signals control a much higher pixel activation voltage. Although the invention was created with field-emission displays in mind, the technique may be used in any matrix-addressable display (e.g. vacuum fluorescent, electro-luminescent, or plasma-type displays) where high pixel activation voltages must be switched. In a preferred embodiment field emission display, emitter-to-grid voltage differential is maintained near zero during non-emission periods, and is raised to a level sufficient to cause emission by grounding pixel emitters at each row and column intersection through a pair of series-connected field-effect transistors (FETs). The emitter base electrode of each emitter node is coupled to the grid via a current-limiting transistor. Display brightness control is accomplished by varying the gate voltages of either FET, such that emission current can be adjusted. In addition, a fusible link is placed in series with the grounding path through the series-connected FETs. Gray scale shading is accompanied by varying the duty cycle of pixel actuation time as a percentage of frame time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.