Method for manufacturing an MOS transistor
US5212104A · kind A · utility
6Cited by
2References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 9, 1992 |
| Grant date | May 18, 1993 |
| Priority date | — |
| Expiry date | Mar 9, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/314
Abstract
A method for the manufacture of an MOS transistor. A channel region is produced by selective epitaxy on a substrate (1) doped with a first conductivity type, said channel region containing a delta-shaped layer (5) doped with the first conductivity type. Source region (13) and drain region (14) are formed, in particular, by drive-out from a doped glass layer (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.