System and method for reducing ground bounce in integrated circuit output buffers
US5214320A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 1992 |
| Grant date | May 25, 1993 |
| Priority date | — |
| Expiry date | Jun 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/163
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for reducing the amount of ground bounce in output buffer circuits. The invention includes a first control circuit to control the amount of time it takes for a pull-up FET to be turned on, and thus the amount of time it takes for an output signal of the output buffer circuit to transition from a low to a high state. The invention also includes a second control circuit to control the amount of time it takes to turn on a pull down FET and thus the amount of time it takes for the output signal of the output buffer circuit to transition from a high to a low state. First and second control circuits each include an additional FET for controlling the amount of current supplied to the pull-up and pull-down FET, respectively. Each additional FET is driven by a voltage reference signal which is above the threshold of the additional FET. Thus, the additional FET is not fully on or off, but introduces a resistance into the control circuit, thus decreasing the amount of current supplied to the pull-up and pull-down FETs. Since the current amount of current provided to the final output FETs is reduced, their turn-on time is slower and thus the switching time of output buffer …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.