Data prefetching based on store information in multi-processor caches
US5214766A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 19, 1992 |
| Grant date | May 25, 1993 |
| Priority date | — |
| Expiry date | Aug 19, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism using CH.sub.Loc (change-local) type information is used for data prefetch (D-prefetch) decision making. This information is stored in history tables H, there being one such table for each central processor (CP) at, for example, the buffer control element (BCE). For each line L, H[L] indicates the information for L in H. Two different types of histories may be kept at H: PA1 (1) Cross-interrogate (XI)-invalidates--At each H[L], there is recorded whether L was XI-invalidated without refetching. PA1 (2) CH.sub.Loc --At each H[L], there is also recorded local-change history, i.e., whether L was stored into since the last fetch. It is also possible to keep a global H at the storage control element (SCE). In this case, the SCE maintains a table I recording, for each line L, information I[L] recording whether L involved XI-invalidates during the last accesses by a CP. Upon a cache miss to L from a processor CP.sub.i, the SCE prefetches some of those lines that involved XI-invalidates (indicated by I) into cache C.sub.i, if missing there. The management of table I is simple. When an XI-invalidate on L occurs, e.g., upon a store or an EX fetch, the corresponding entry is set. W…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.