Integrated circuit memory devices with high angle implant around top of trench to reduce gated diode leakage
US5216265A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1991 |
| Grant date | Jun 1, 1993 |
| Priority date | — |
| Expiry date | Dec 18, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.