Semiconductor memory device having a peripheral wall at the boundary region of a memory cell array region and a peripheral circuit region

US5218219A · kind A · utility

Assignee

• Mitsubishi Electric Corporation · JP

Inventors

• Natsuo Ajika · Kasai, JP
• Hideaki Arima · Kasai, JP
• Kaoru Motonami · Kasai, JP
• Atsushi Hachisuka · Kasai, JP
• Tomonori Okudaira · Kasai, JP

Key dates

• Filing date: Apr 4, 1991
• Grant date: Jun 8, 1993
• Expiry date: Apr 4, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/318

Abstract

A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.