Semiconductor device having a multilayer leadframe with full power and ground planes
US5220195A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1991 |
| Grant date | Jun 15, 1993 |
| Priority date | — |
| Expiry date | Dec 19, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device (10) has a multilayer leadframe (14) with two full voltage planes, specifically an upper voltage plane (16) and a lower voltage plane (18). A semiconductor die (12) is mounted to the upper voltage plane. Bond pads (13) of the die are electrically coupled to appropriate leads (20a, 20b, and 20c) using conductive wires (22). Upper voltage plane (16) is provided with at least one opening (28) to allow passage of a conductive wire through the opening in order to electrically couple a bond pad or a lead to lower voltage plane (18). The voltage planes are attached to the leadframe using welded conductive tabs (24), an electrically insulating adhesive layer (26), or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.