Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
US5220199A · kind A · utility
45Cited by
2References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1991 |
| Grant date | Jun 15, 1993 |
| Priority date | — |
| Expiry date | Jun 13, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-layered structure of wirings on a semiconductor substrate has been employed in conjunction with the increase in the integration density of semiconductor integrated circuit devices. In the invention, dummy patterns made of the same material as an Al wiring layer for compensating for any step or level gradation are disposed in the regions below bump electrodes and in the proximity thereof in order to reduce any defects inherent to a multi-layered structure that occur in CCB bump electrodes formed on the multi-layered wirings and at pads as the base layer of the former.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.