Sense amplifier pulldown circuit for minimizing ground noise at high power supply voltages
US5220221A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 6, 1992 |
| Grant date | Jun 15, 1993 |
| Priority date | — |
| Expiry date | Mar 6, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pulldown circuit for a sense amplifier includes an output node for coupling to a common node of one or more sense amplifiers in a DRAM. The drain of an N-channel pulldown transistor is coupled to the output node. Additional pulldown circuitry includes an inverter, a P-channel transistor, and a bias circuit coupled to the supply voltage for providing a gate signal to the gate of the N-channel pulldown transistor. The slope of the gate signal is substantially insensitive to the value of the power supply voltage, thus changing the rate at which the common node is discharged to the enabling ground level. Since the rate of discharge is substantially the same at higher power supply voltages, the instantaneous current is substantially the same, which in turn prevents the internal ground lines from developing an additional undesirable ground voltage increase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.