Programmable logic array with internally generated precharge and evaluation timing
US5221867A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1991 |
| Grant date | Jun 22, 1993 |
| Priority date | — |
| Expiry date | Oct 11, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Timing signals governing the precharge and evaluation phases of a PLA are generated by internal circuitry so that the PLA can be maintained in a fully static mode without destroying data integrity and without dissipating a significant amount of power. "Dummy" lines connected at every programmable intersection are added to the PLA to provide a measure of the maximum propagation delay. The evaluation phase of the PLA is terminated closely following the maximum propagation delay and precharging is begun soon thereafter. The timing ensures that evaluation completes, valid data is latched and the PLA is returned to a precharge condition even if the phase clock signals are suspended and regardless of the states of the phase clock signals when suspended.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.