Sundari Mitra
21Patents
12h-index
13Co-inventors
78Inventor score
Filing activity: Oct 11, 1991 → Jun 25, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8601423B1 | Asymmetric mesh NoC topologies | Electricity | 92 | Active |
| US8819611B2 | Asymmetric mesh NoC topologies | Electricity | 55 | Active |
| US5274678A | Clock switching apparatus and method for computer systems | Electricity | 46 | Expired |
| US5221867A | Programmable logic array with internally generated precharge and evaluation timing | Electricity | 36 | Expired |
| US5668490A | Flip-flop with full scan capability | Electricity | 34 | Expired |
| US8885510B2 | Heterogeneous channel capacities in an interconnect | Electricity | 29 | Active |
| US9244880B2 | Automatic construction of deadlock free interconnects | Electricity | 26 | Active |
| US5481697A | An apparatus for providing a clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies | Electricity | 23 | Expired |
| US9253085B2 | Hierarchical asymmetric mesh with virtual routers | Electricity | 22 | Active |
| US8819616B2 | Asymmetric mesh NoC topologies | Electricity | 17 | Active |
| US6081022A | Clock distribution network with efficient shielding | Electricity | 14 | Expired |
| US5850150A | Final stage clock buffer in a clock distribution network | Physics | 13 | Expired |
| US9009648B2 | Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification | Electricity | 12 | Active |
| US9130856B2 | Creating multiple NoC layers for isolation or avoiding NoC traffic congestion | Electricity | 7 | Active |
| US5880607A | Clock distribution network with modular buffers | Physics | 6 | Expired |
| US6157237A | Reduced skew control block clock distribution network | Physics | 6 | Expired |
| US5994765A | Clock distribution network with efficient shielding | Electricity | 3 | Expired |
| US9007920B2 | QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes | Electricity | 2 | Active |
| US10355996B2 | Heterogeneous channel capacities in an interconnect | Electricity | 1 | Active |
| US9185026B2 | Tagging and synchronization for fairness in NOC interconnects | Electricity | 1 | Active |
| US9774498B2 | Hierarchical asymmetric mesh with virtual routers | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.