Method for producing a layered capacitor structure for a dynamic random access memory device
US5223448A · kind A · utility
51Cited by
6References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 18, 1991 |
| Grant date | Jun 29, 1993 |
| Priority date | — |
| Expiry date | Jul 18, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
An improved method and resulting structures for producing a layered capacitor structure of memory cell of a DRAM device wherein a doped polysilicon spacer operates as a dopant source for an overlying polysilicon layer on the vertical and sharply inclined surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.