Logic level shifter for 3 volt CMOS to 5 volt CMOS or TTL
US5223751A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1991 |
| Grant date | Jun 29, 1993 |
| Priority date | — |
| Expiry date | Oct 29, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic level shifter characterized by a first inverting stage which shifts an input signal downwardly to a lower level, and a second inverting stage which shifts the lower level upwardly to an output signal level which is greater than the input signal level. Feedback from the output is used to virtually eliminate static current drain when the input logic level is 0. The method of the invention involves downwardly shifting an input range of voltages to a lower range of voltages, and then upwardly shifting the lower range of voltages to an output range of voltages which is greater than the input range of voltages. There is preferably a first inversion in the downward shift and a second inversion in the upward shift. A sensing step senses the output voltage to reduce the static current consumed by the process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.