Method of reducing hot-electron degradation in semiconductor devices
US5229311A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1992 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Mar 25, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of reducing the degradation effects associated with avalanche injection or tunnelling of hot-electrons in a field-effect semiconductor device is disclosed. The method of the present invention includes covering the active regions of the semiconductor device with a protective titanium barrier layer which is deposited directly underneath the ordinary metalization layers used for connecting the devices to bit and word lines within an array. Inclusion of the titanium barrier layer in a flash memory device results in a substantial improvement in the erasetime push-out and reduces excess charge loss normally associated with hot-electron devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.