Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation
US5229314A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 1992 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Aug 6, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/611
Abstract
A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.