Method for testing a sequential circuit by splicing test vectors into sequential test pattern
US5230001A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1991 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Mar 8, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318392
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
During application of a sequence of design verification patterns at the primary input pins of a sequential circuit IC, a test vector is spliced between patterns to test for a fault condition. As design verification patterns are applied in sequence, the state of the sequential circuit changes. To test for a select fault condition, the sequential circuit needs to be in a desired state. While in such desired state, a test vector is applied and select internal circuit element responses are monitored. If the desired state occurs during a sequence of design verification patterns, then the test vector is applied between successive patterns before the IC clock has a transition. By applying the test signal, monitoring the response, then reapplying the design verification pattern before the clock changes, the IC subsequent state which would occur had the test vector been omitted still occurs. If a desired state does not occur during the sequence of design verification patterns, then a select state similar to the desired state is identified. When such select state occurs, control signals are applied through internal test points to force a state change to the desired state. Thereafter, the app…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.