Process for thin film interconnect
US5231751A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1991 |
| Grant date | Aug 3, 1993 |
| Priority date | — |
| Expiry date | Oct 29, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/31681
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This invention relates generally to a structure and process for thin film interconnect, and more particularly to a structure and process for a multilayer thin film interconnect structure with improved dimensional stability and electrical performance. The invention further relates to a process of fabrication of the multilayer thin film structures. The individual thin film structure is termed a compensator, and functions as both a ground/reference plane and as a stabilizing entity with regard to dimensional integrity. The compensator is comprised primarily of a metal sheet having a metallized via pattern and high-temperature stable polymer as an insulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.