Fault mapping apparatus for memory
US5233614A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 1991 |
| Grant date | Aug 3, 1993 |
| Priority date | — |
| Expiry date | Jan 7, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory fault mapping apparatus detects faults generated in a memory array during on-line operation. As the memory array is randomly accessed, single bit error are detected, corrected, and mapped into an error memory. The errors may be mapped in an error memory having a memory location for each memory of the memory array or alternatively, by grouping memories together and when the errors generated by any one group exceeds a predetermined threshold of errors, testing only the memories in that group off-line. By grouping the memories a substantial reduction in the amount of error memory required can be achieved. A SEC/DED syndrome generator detects single and double bit errors, correcting the single bit errors while providing an indication of which memory generated the error. An error memory stores error counts for the memory array, each error count indicating the number of errors for a specific memory or a group of memories. The error counts are incremented by loading the error count into a counter for incrementing then writing the incremented error count back to the error memory location from which it was read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.