Process for the manufacture of an interconnect circuit
US5234536A · kind A · utility
10Cited by
17References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1992 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Apr 1, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1545
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for the manufacture of an electronic circuit is provided. A substrate is provided with an indexing means and personality windows by etching. An adhesive is deposited on one surface of the substrate to coat at least those regions to be laminated to a metallic foil. The foil is bonded to the nonconductive substrate and patterned into a plurality of circuit traces. These steps may be repeated a plurality of time for a multi-metal layer structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.