Method of manufacturing semiconductor IC using selective poly and EPI silicon growth
US5234845A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1992 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Mar 30, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/969
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Herein disclosed is an improved bipolar transistor manufacturing method which adopts an EBT (Epitaxial Base Transistor) structure using an SPESG (Selective Poly-and-Epitaxial-Silicon Growth) technique. Specifically, the method of manufacturing a bipolar transistor according to the present invention comprises the steps of: forming an isolation oxide layer to enclose an active region of a single crystal semiconductor substrate and to have a lower surface than that of the substrate of said active region; simultaneously forming a single crystal silicon layer over the substrate surface of said active region and a polycrystal silicon layer to become integral with said single crystal silicon layer over the surface of said isolation oxide layer by simultaneously growing silicon films over the substrate surface of said active region and the surface of said isolation oxide layer; and forming an active region of a semiconductor element in said single crystal silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.