Method for determining planarization endpoint during chemical-mechanical polishing
US5234868A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1992 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Oct 29, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A moat is preferably created in a region of an insulation layer on a wafer that will be destroyed when the wafer is cut. The integrated circuit includes a first metal pattern in an active region and a second metal pattern on the moat island. An insulating layer is conformally deposited and chemical-mechanical polishing is performed thereon. The polish rate above the second metal pattern is significantly higher than above the first metal pattern. Polishing is monitored and ended when the second metal pattern is exposed, achieving planarization of the top surface in the active region of the integrated circuit. Monitoring may be visual or electrical. For visual monitoring, the second metal pattern preferably comprises a visually noticeable metal in relation to the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.