Semiconductor memory with pad electrode and bit line under stacked capacitor
US5235199A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1992 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Feb 7, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/908
Abstract
A semiconductor memory has many memory cells each comprising a transistor and a capacitor. In each memory cell, one of the source and drain regions of the transistor is connected to a bit line. The bit line is formed above the transistor. The capacitor comprises a first capacitor electrode formed on a substrate and a second capacitor electrode formed on an insulation film coated on the surface of the first capacitor electrode. The first capacitor electrode is connected to the other of the source and drain regions of the transistor. The first capacitor electrode is formed above the bit line. To manufacture such a semiconductor memory, each memory cell region is separately formed on the surface of a substrate. A gate insulation film is formed on the memory cell region. A gate electrode is formed on the gate insulation film. The gate electrode is used as a mask to dope the substrate with impurities to form source and drain regions of a transistor. A bit line is formed and connected to one of the source and drain regions. A first capacitor electrode is formed above the bit line and connected to the other of the source and drain regions. An insulation film is formed on the surface of th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.