Reducing clock skew in large-scale integrated circuits
US5235521A · kind A · utility
25Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1991 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Oct 8, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.