Digital processor for two's complement computations
US5235537A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1991 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Oct 29, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital processor for two's complement computations incorporates an array of multiplier cells each having the one-bit gated full adder logic function. The array has nearest-neighbour connections containing clock-activated latches for bit propagation. On each clock cycle, the cells receive input data, carry and cumulative sum bits. Each cell adds the carry and cumulative sum bits to the product of the data bit and a respective digit associated with the relevant cell. Data bits pass along array rows and sum bits accumulate in cascade down array columns. Carry bits are recirculated. Each coefficient digit is expressed as a sign bit and at least one magnitude bit consisting of or including a level bit. Each cell includes logic gates responsive to the sign and level bits, and carry a feedback latch and multiplier combination responsive to a least significant data bit flag to substitute the sign bit for a carry feedback bit. Each coefficient digit may include an additional magnitude bit expressed as a shift bit and employed to select multiplicand data bit significance, the logic gates being responsive to flag bits to eliminate unwanted sign extension bit products. The processor may inc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.