Metal interconnection layer having reduced hillock formation in semi-conductor device and manufacturing method therefor
US5236866A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1992 |
| Grant date | Aug 17, 1993 |
| Priority date | — |
| Expiry date | Oct 13, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/937
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having multilayer interconnections with reduced formation of hillocks is provided. An Al wiring layer formed on a substrate is patterned for Al wirings. Impurity ions such as Al, Ar, As, P and Sb or the like are implanted on the entire surface including sidewalls of the provided Al wirings. Such impurity ions are implanted to entire surface including sidewalls of the Al wirings, the grain size of granular material at sidewalls of the Al wirings can be made smaller than that of the granular material at inner portions of the metal wirings. As the grain size is reduced, the size of the generated hillocks is reduced. Consequently, short circuits between Al wirings in the same layer can be prevented, enabling provision of highly reliable and highly integrated semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.