High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device
US5237676A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 1989 |
| Grant date | Aug 17, 1993 |
| Priority date | — |
| Expiry date | Jan 13, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system bus includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.