Ravi Kumar Arimilli
508Patents
40h-index
86Co-inventors
93Inventor score
Filing activity: Jan 13, 1989 → Jun 15, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6748518B1 | Multi-level multiprocessor speculation mechanism | Physics | 98 | Expired |
| US6029217A | Queued arbitration mechanism for data processing system | Physics | 90 | Expired |
| US5895495A | Demand-based larx-reserve protocol for SMP system buses | Physics | 83 | Expired |
| US6405289B1 | Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response | Physics | 82 | Expired |
| US5613153A | Coherency and synchronization mechanisms for I/O channel controllers in a data processing system | Physics | 79 | Expired |
| US6691220B1 | Multiprocessor speculation mechanism via a barrier speculation flag | Physics | 74 | Expired |
| US6591321B1 | Multiprocessor system bus protocol with group addresses, responses, and priorities | Physics | 67 | Expired |
| US6625660B1 | Multiprocessor speculation mechanism for efficiently managing multiple barrier operations | Physics | 64 | Expired |
| US6880073B2 | Speculative execution of instructions and processes before completion of preceding barrier operations | Physics | 63 | Expired |
| US6018791A | Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states | Physics | 63 | Expired |
| US7840703B2 | System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture | Electricity | 62 | Active |
| US6393528B1 | Optimized cache allocation algorithm for multiple speculative requests | Physics | 60 | Expired |
| US6473833B1 | Integrated cache and directory structure for multi-level caches | Physics | 57 | Expired |
| US7213248B2 | High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system | Physics | 57 | Expired |
| US6848003B1 | Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response | Physics | 55 | Expired |
| US6829762B2 | Method, apparatus and system for allocating and accessing memory-mapped facilities within a data processing system | Physics | 54 | Expired |
| US7073043B2 | Multiprocessor system supporting multiple outstanding TLBI operations per partition | Physics | 54 | Expired |
| US8351200B2 | Convergence of air water cooling of an electronics rack and a computer room in a single unit | Electricity | 53 | Active |
| US6408362B1 | Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data | Physics | 51 | Expired |
| US6434669B1 | Method of cache management to dynamically update information-type dependent cache policies | Physics | 51 | Expired |
| US6829698B2 | Method, apparatus and system for acquiring a global promotion facility utilizing a data-less transaction | Emerging Cross-Sectional Technologies | 51 | Expired |
| US6785776B2 | DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism | Physics | 49 | Expired |
| US6058456A | Software-managed programmable unified/split caching mechanism for instructions and data | Physics | 48 | Expired |
| US6192458A | High performance cache directory addressing scheme for variable cache sizes utilizing associativity | Physics | 47 | Expired |
| US6192451A | Cache coherency protocol for a data processing system including a multi-level memory hierarchy | Physics | 47 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.