High voltage random-access memory cell incorporating level shifter
US5239503A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1992 |
| Grant date | Aug 24, 1993 |
| Priority date | — |
| Expiry date | Jun 17, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level-shifting static random access memory cell includes a first stage having a first P-Channel MOS transistor having its source connected to a high voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-channel MOS transistor is connected to a VSS power supply rail. A second stage comprises a second P-Channel MOS transistor having its source connected to the high voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-channel MOS transistor is connected to VSS. The gates of the first and second P-Channel MOS transistors are cross coupled and the gates of the second and fourth N-Channel MOS transistors are cross coupled. The gates of the first and third N-channel MOS transistors are connected together to power supply rail V.sub.DD, usually 5 volts. The first and second P-channel MOS transistors are formed in an n-well …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.