Adi Srinivasan
26Patents
13h-index
13Co-inventors
74Inventor score
Filing activity: Jun 17, 1992 → Jun 16, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6242767A | Asic routing architecture | Electricity | 103 | Expired |
| US6698006B1 | Method for balanced-delay clock tree insertion | Physics | 49 | Expired |
| US8286111B2 | Thermal simulation using adaptive 3D and hierarchical grid mechanisms | Physics | 36 | Active |
| US7823102B2 | Thermally aware design modification | Electricity | 35 | Active |
| US6014038A | Function block architecture for gate array | Electricity | 34 | Expired |
| US6754877B1 | Method for optimal driver selection | Physics | 32 | Expired |
| US6701505B1 | Circuit optimization for minimum path timing violations | Physics | 29 | Expired |
| US5301147A | Static random access memory cell with single logic-high voltage level bit-line and address-line drivers | Electricity | 27 | Expired |
| US6701507B1 | Method for determining a zero-skew buffer insertion point | Physics | 25 | Expired |
| US6223313A | Method and apparatus for controlling and observing data in a logic block-based asic | Physics | 23 | Expired |
| US6701506B1 | Method for match delay buffer insertion | Electricity | 17 | Expired |
| US8019580B1 | Transient thermal analysis | Physics | 13 | Active |
| US5257239A | Memory cell with known state on power-up | Physics | 13 | Expired |
| US6611932B2 | Method and apparatus for controlling and observing data in a logic block-based ASIC | Physics | 12 | Expired |
| US7003741B2 | Method for determining load capacitance | Physics | 12 | Expired |
| US5400294A | Memory cell with user-selectable logic state on power-up | Physics | 11 | Expired |
| US5406138A | Programmable interconnect architecture using fewer storage cells than switches | Electricity | 11 | Expired |
| US6954917B2 | Function block architecture for gate array and method for forming an asic | Electricity | 10 | Expired |
| US7222318B2 | Circuit optimization for minimum path timing violations | Physics | 8 | Expired |
| US5315545A | High-voltage five-transistor static random access memory cell | Physics | 8 | Expired |
| US5319261A | Reprogrammable interconnect architecture using fewer storage cells than switches | Electricity | 6 | Expired |
| US5239503A | High voltage random-access memory cell incorporating level shifter | Physics | 6 | Expired |
| US7353471B1 | Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance | Physics | 6 | Expired |
| US6690194B1 | Function block architecture for gate array | Electricity | 6 | Expired |
| US5367482A | High voltage random-access memory cell incorporation level shifter | Physics | 4 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.