High-density erasable programmable logic device architecture using multiplexer interconnections
US5241224A · kind A · utility
166Cited by
10References
19Claims
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Assignee
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Key dates
| Filing date | Apr 25, 1991 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | Apr 25, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.