Floating point arithmetic unit with size efficient pipelined multiply-add architecture
US5241493A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1991 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | Dec 16, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture and method relating to a floating point operation which performs the mathematical computation of A*B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A*B+C while using a full adder of three-quarters normal size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.