Method for parallel instruction execution in a computer
US5241636A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 1990 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | Feb 14, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for parallel instruction execution in a computer is described. If the computer is executing in the single-instruction mode and the computer encounters a first type of instruction with a dual-instruction mode bit having a first value, then one more single instruction is executed before dual-instruction mode instruction execution begins. The first type of instruction is an instruction having a dual-instruction mode bit. The dual-instruction mode instruction execution occurs in parallel. If the computer is executing in the dual-instruction mode and the computer encounters the first type of instruction with the dual-instruction mode bit having a second value, wherein the second value is different from the first value, then one more dual instruction is executed before single-instruction mode instruction execution resumes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.