Method for planarized isolation for CMOS devices
US5244827A · kind A · utility
19Cited by
0References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1991 |
| Grant date | Sep 14, 1993 |
| Priority date | — |
| Expiry date | Oct 31, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming field oxide regions includes the formation of cavities in a semiconductor substrate. A layer of thermal oxide is then grown on the substrate. A layer of planarizing material is deposited over the device, filling the cavities. The planarizing layer is etched back to expose a portion of the cavities. A conformal layer of undoped oxide or a layer of polycrystalline silicon that is converted to oxide is deposited over the device, followed by a second layer of planarizing material, The planarizing material and conformal layer are then etched back to expose the active areas in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.