Integrated delay line
US5245231A · kind A · utility
65Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1991 |
| Grant date | Sep 14, 1993 |
| Priority date | — |
| Expiry date | Dec 30, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay line within an integrated circuit and calibrated by an external time period (calibration clock). The speed of devices in the integrated circuit is assessed using the calibration clock, and this speed then controls how many delay cells within the delay line an input must traverse to trigger the delayed output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.