Darius D. Gaskins
96Patents
18h-index
21Co-inventors
84Inventor score
Filing activity: May 25, 1990 → Nov 29, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5261068A | Dual path memory retrieval system for an interleaved dynamic RAM memory unit | Physics | 207 | Expired |
| US5802356A | Configurable drive clock | Physics | 143 | Expired |
| US5245231A | Integrated delay line | Electricity | 65 | Expired |
| US7441064B2 | Flexible width data protocol | Emerging Cross-Sectional Technologies | 60 | Expired |
| US5463643A | Redundant memory channel array configuration with data striping and error correction capabilities | Physics | 50 | Expired |
| US5623700A | Interface circuit having zero latency buffer memory and cache memory information transfer | Physics | 45 | Expired |
| US6681311B2 | Translation lookaside buffer that caches memory type information | Physics | 43 | Expired |
| US5903911A | Cache-based computer system employing memory control circuit and method for write allocation and data prefetch | Physics | 40 | Expired |
| US5432735A | Ternary storage dynamic RAM | Physics | 40 | Expired |
| US5623633A | Cache-based computer system employing a snoop control circuit with write-back suppression | Physics | 36 | Expired |
| US5781926A | Method and apparatus for sub cache line access and storage allowing access to sub cache lines before completion of line fill | Physics | 33 | Expired |
| US6549985B1 | Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processor | Physics | 29 | Expired |
| US5708794A | Multi-purpose usage of transaction backoff and bus architecture supporting same | Physics | 29 | Expired |
| US5761725A | Cache-based computer system employing a peripheral bus interface unit with cache write-back suppression and processor-peripheral communication suppression for data coherency | Physics | 28 | Expired |
| US5809562A | Cache array select logic allowing cache array size to differ from physical page size | Physics | 26 | Expired |
| US7814350B2 | Microprocessor with improved thermal monitoring and protection mechanism | Emerging Cross-Sectional Technologies | 25 | Active |
| US5477551A | Apparatus and method for optimal error correcting code to parity conversion | Physics | 24 | Expired |
| US5640517A | Method and apparatus for masters to command a slave whether to transfer data in a sequential or non-sequential burst order | Physics | 20 | Expired |
| US5835929A | Method and apparatus for sub cache line access and storage allowing access to sub cache lines before completion of a line fill | Physics | 18 | Expired |
| US7411840B2 | Sense mechanism for microprocessor bus inversion | Physics | 17 | Active |
| US7290156B2 | Frequency-voltage mechanism for microprocessor power management | Emerging Cross-Sectional Technologies | 17 | Expired |
| US6553473B1 | Byte-wise tracking on write allocate | Physics | 16 | Expired |
| US5590338A | Combined multiprocessor interrupt controller and interprocessor communication mechanism | Physics | 15 | Expired |
| US7358758B2 | Apparatus and method for enabling a multi-processor environment on a bus | Physics | 14 | Active |
| US5357622A | Apparatus for queing and storing data writes into valid word patterns | Physics | 14 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.