Apparatus for multiplying operands
US5245564A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1991 |
| Grant date | Sep 14, 1993 |
| Priority date | — |
| Expiry date | May 10, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5523
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an apparatus and method for computing inverses and square roots a highly accurate initial approximation is computed using a second order polynomial equation, the coefficients of which are stored in a ROM. The most significant bits of an operand are used to address a ROM to select coefficients, providing different coefficients for different operand ranges. The remaining lesser significant operand bits are used in the computation; the coefficient values already account for the bits used to address them. The result is in single precision accuracy. For double precision, the polynomial results are used as the first approximation for a Newton-Raphson iteration. The multiplier has a split array mode to speed up the calculation of the polynomial, whereby two lesser precision values can be computed at once. The size of the coefficients is tailored to produce the proper precision result for each of the elements of Ax.sup.2 +Bx+C. Separate values for the coefficients A, B, and C must be stored for the 1/x approximation and for the 1/.sqroot.x approximation. Also to speed up the multiplier, the multiplier can accept one operand in carry/save format, by providing Booth recoder logic which ca…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.