Memory cell array divided type multi-port semiconductor memory device
US5249165A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 6, 1992 |
| Grant date | Sep 28, 1993 |
| Priority date | — |
| Expiry date | Mar 6, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array divided type multi-port memory device having random access circuit and serial access circuit, including: a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being disposed in a column direction at a predetermined pitch, each the cell array section having a plurality of word lines and bit lines, the word lines being connected to the memory cells disposed in a row direction for selection of the connected memory cells, and the bit lines being connected to the memory cells disposed in a column direction for data transfer to and from the selected memory cells; a row decoder for activating a desired one of the word lines; sense amplifier provided for each the bit line for sensing data read out to each the bit line; a RAM port connected to the bit lines via RAM transfer gates; a column decoder for selectively turn on/off the RAM transfer gates; a plurality of data transfer lines each having a data transfer gate at the intermediate position thereof, the data transfer lines being connected to the bit lines and formed on a layer different from layers of the word lines and bit lines; dat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.