Low skew CMOS clock divider
US5249214A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1992 |
| Grant date | Sep 28, 1993 |
| Priority date | — |
| Expiry date | Jun 30, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15066
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-skew CMOS clock divider circuit for providing tracking of the divide-by-one and divide-by-two output signals obtained from a source of master clock pulses is fabricated using two matched flip-flops externally wired as divide-by-two devices. Coincidence gates are coupled with the outputs of the flip-flops to produce the desired divide-by-one and divide-by-two output signals in a manner such that the signals in each path pass through substantially identical circuit components, Thus, any delays encountered are the same in both circuit paths. In this manner, skew between the edges of the divide-by-two and divide-by-one clock signals is significantly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.