Discretionary gettering of semiconductor circuits
US5250445A · kind A · utility
64Cited by
11References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 1992 |
| Grant date | Oct 5, 1993 |
| Priority date | — |
| Expiry date | Jan 17, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer (32) is patterned to have gettering areas (36-38) selectively positioned proximate devices (44-46) which require gettering. The areas (36-38) comprise germanium-doped silicon having a germanium concentration of approximately 1.5%-2.0%. The germanium creates a lattice mismatch between the substrate (32) and an epitaxial layer (34) which is sufficient to produce defects capable of gettering contaminants. The gettering areas (36-38) may be formed by selective deposition, selective etching, ion-implantation or selective diffusion techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.