Method for forming thickened source/drain contact regions for field effect transistors
US5250454A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1992 |
| Grant date | Oct 5, 1993 |
| Priority date | — |
| Expiry date | Dec 10, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0275
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for the self-aligned thickening of the source and drain contact regions (24,26) in which an amorphous silicon layer (40) is deposited over the gate (16), source contact region (24), the drain contact region (26), and side wall spacer (20) of an FET being fabricated on a substrate silicon layer (14). The amorphous layer (40) is heated to induce epitaxial growth in the source contact region (24) and drain contact region (26). The induced epitaxial growth of the amorphous silicon thickens these contact regions allowing for the subsequent formation of a highly conductive contact silicide for the cases where the available volume of the silicon in the contact areas is limited. The uncrystallized silicon is removed from the side wall spacer (20) of the gate and other insulating areas by a selective wet etch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.