Witold P. Maszara
60Patents
18h-index
37Co-inventors
84Inventor score
Filing activity: Feb 14, 1991 → Mar 18, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6184112A | Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile | Electricity | 127 | Expired |
| US6060364A | Fast Mosfet with low-doped source/drain | Electricity | 124 | Expired |
| US6680240B1 | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide | Electricity | 118 | Expired |
| US7078299B2 | Formation of finFET using a sidewall epitaxial layer | Emerging Cross-Sectional Technologies | 103 | Expired |
| US6955969B2 | Method of growing as a channel region to reduce source/drain junction capacitance | Electricity | 88 | Expired |
| US6245636A | Method of formation of pseudo-SOI structures with direct contact of transistor body to the substrate | Electricity | 63 | Expired |
| US6586808B1 | Semiconductor device having multi-work function gate electrode and multi-segment gate dielectric | Electricity | 54 | Expired |
| US6630720B1 | Asymmetric semiconductor device having dual work function gate and method of fabrication | Electricity | 51 | Expired |
| US5965917A | Structure and method of formation of body contacts in SOI MOSFETS to elimate floating body effects | Electricity | 41 | Expired |
| US6815297B1 | Ultra-thin fully depleted SOI device and method of fabrication | Electricity | 39 | Expired |
| US6204138A | Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects | Electricity | 37 | Expired |
| US6444534B1 | SOI semiconductor device opening implantation gettering method | Electricity | 32 | Expired |
| US8466034B2 | Method of manufacturing a finned semiconductor device structure | Electricity | 25 | Active |
| US8673718B2 | Methods of forming FinFET devices with alternative channel materials | Electricity | 22 | Active |
| US5250454A | Method for forming thickened source/drain contact regions for field effect transistors | Electricity | 20 | Expired |
| US8580642B1 | Methods of forming FinFET devices with alternative channel materials | Electricity | 19 | Active |
| US7871873B2 | Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material | Electricity | 19 | Active |
| US8859389B2 | Methods of making fins and fin field effect transistors (FinFETs) | Electricity | 18 | Active |
| US6362063B1 | Formation of low thermal budget shallow abrupt junctions for semiconductor devices | Electricity | 18 | Expired |
| US6238960A | Fast MOSFET with low-doped source/drain | Electricity | 17 | Expired |
| US8101486B2 | Methods for forming isolated fin structures on bulk semiconductor material | Electricity | 15 | Active |
| US6599831B1 | Metal gate electrode using silicidation and method of formation thereof | Electricity | 15 | Expired |
| US6399452B1 | Method of fabricating transistors with low thermal budget | Electricity | 15 | Expired |
| US6492209B1 | Selectively thin silicon film for creating fully and partially depleted SOI on same wafer | Electricity | 14 | Expired |
| US8716074B2 | Methods for forming isolated fin structures on bulk semiconductor material | Electricity | 14 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.