Circuitry and method for latching a logic state
US5250852A · kind A · utility
45Cited by
3References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1992 |
| Grant date | Oct 5, 1993 |
| Priority date | — |
| Expiry date | Dec 9, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and circuitry are provided for latching a logic state. A first signal (64) indicates a logic state of an input signal (D) in response to a first transition of a clock signal (72). A second signal (68) indicates a logic state of the first signal (64) in response to a second transition of the clock signal (72). An output signal (Q) indicates the logic state of the first signal (64) in response to the second transition and indicates a logic state of the second signal (68) in response to the first transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.