Boundary cells for improving retention time in memory devices
US5251168A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1991 |
| Grant date | Oct 5, 1993 |
| Priority date | — |
| Expiry date | Jul 31, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
By placing boundary cells within areas of discontinuity of a memory array, such as in word line strap areas, stress on edge cells of the memory array is reduced; the reduction of stress improves leakage characteristics and pause-refresh capabilities of edge cells. The boundary cells may further be laid out in the areas of discontinuity with the same pattern as the memory array. Some of the boundary cells may be electrically biased to act as minority carrier sinks. By collecting minority carriers that otherwise may be attracted to edge cells of the memory array, the leakage characteristics of the edge cells and their pause-refresh capabilities are further enhanced. The boundary cells are particularly useful in improving leakage characteristics of dynamic random access memory devices of the trench capacitor type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.