Method for manufacturing a CMOS device having twin wells and an alignment key region

US5252510A · kind A · utility

Assignee

• Hyundai Electronics Industries Co. Ltd. · KR

Inventors

• Dai H. Lee · Seoul, KR
• Hyung L. Ji · Suwon-si, KR

Key dates

• Filing date: Apr 29, 1992
• Grant date: Oct 12, 1993
• Expiry date: Apr 29, 2012

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/07

Abstract

A method for manufacturing a CMOS semiconductor device having twin wells is disclosed. The method of manufacturing the CMOS device comprises the following. A silicon substrate is provided. A thick oxide layer is deposited and a first photoresist layer is coated sequentially on the silicon substrate. Then an N-well mask pattern is formed by removing a portion of the first photoresist layer, thereby defining an alignment-key region and N-well region and forming a thin oxide layer on such regions. An N-type impurity implantion process is then performed through exposed portions of the thin oxide layer into the silicon substrate, and the first photoresist layer portions remaining on the thick oxide layer are removed, to thereby expose the entire surface of the thick oxide layer. A second photoresist layer is coated on the entire surface of the oxide layer. Then a P-well mask pattern is formed by removing portions of the second photoresist layer, thereby defining a P-well region and forming a thin oxide layer thereon. A P-type impurity diffusion process is performed through expose portions of the thin oxide layer into the silicon substrate, and the remaining portions of the second photor…