Isolation method in a semiconductor device
US5252511A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 1992 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | Jan 17, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76216
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An isolation method in a semiconductor device which includes the steps of growing a pad oxide layer on a semiconductor substrate, depositing a polysilicon layer and a first silicon nitride layer on the pad oxide layer, removing and patterning the first silicon nitride layer to define an active region and a field region, depositing a second silicon nitride layer and a thick oxide layer, forming oxide spacers and nitride spacers, ion-implanting impurities, removing the oxide spacers, growing a field oxide layer, and sequentially removing the first silicon nitride layer, the nitride spacers, the polysilicon layer, and the pad oxide layer. This method minimizes the bird's beaks regions and increases the effective isolation distance of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.